The present invention relates, in general, to methods of burning in integrated circuits, and more particularly, to a method of burning in integrated circuits in wafer form.
It has long been known that most integrated circuits are subject to a certain infant mortality level caused by latent defects in the devices. In particular, semiconductor memories which have a relatively large die size and use particularly thin gate oxides, are susceptible to infant mortality problems. The bulk of these early failures can be gleaned out by extensively exercising the circuits at high temperature. Exercising the circuit means to apply power to the circuit, and to send data signals to the circuit which activate various portions of the circuit. A memory circuit which comprises thousands or millions of memory cells, for example, is exercised by addressing each memory cell and storing and retrieving data from that cell. When this process is performed at high temperature, it is called burn-in.
Typically, memory circuits are burned-in for 72 or more hours at temperatures exceeding 100.degree. C. In the past, this process has been performed after the circuits have been assembled and tested. The burn-in process requires that the semiconductor packages be loaded into boards of fifty of more units so that they can be exercised in parallel. The boards are then loaded into ovens which control the ambient temperature during burn-in.
Increasingly stringent reliability requirements for semiconductor memories have led many manufacturers to burn-in 100% of their product before shipment. The physical space required to house burn-in ovens for a single manufacturer is enormous. Burn-in of memory circuits alone for a single manufacturer may occupy several city blocks of multi-story buildings. Not only physical space is lost; the power required to heat the burn-in ovens and power the exercising circuits is considerable. This is because integrated circuits from a single wafer once packaged, loaded into boards, and loaded into an oven, will take up several cubic feet of space which must then be heated and cooled to perform the burn-in.
Not only is the physical cost high but labor cost is high also. Loading packaged integrated circuits into boards and removing them from boards is labor intensive and is usually a manual operation. Additionally, after burn-in integrated circuits must be repackaged in shipping tubes or boxes so that they can be further processed or sold. These labor intensive operations can add days to the cycle time of a burn-in operation. Attempts to automate board loading and packaging processes have met with little success, due to the delicate nature of the processes.
Although the burn-in operation is designed to improve the reliability of the integrated circuits, often times it compromises the quality of packaged devices. Manual loading and unloading of integrated circuits often damages leads which extend outside the integrated circuit package. This damage is usually not repairable and results in completely functional devices being rejected for physical quality problems. In addition to lead damage, package damage can occur. Also, handling of packaged integrated circuits increases the chances of damage to the circuits themselves by electrostatic discharge. Although burn-in is necessary to provide the desired reliability, the above-mentioned quality limitations have long been a costly problem for circuit manufacturers.
It has been found that some wafers contain a much higher percentage of burn-in failures than other wafers. It has also been found that wafers with a high reject percentage will have a high reject rate early on in the burn-in process. In the past, though, good and marginal wafers were mixed together so that when the product was packaged and ready for burn-in, there was no way to identify circuits which came from a single wafer. In order to ensure that marginal product was removed during burn-in, longer burn-in times and higher temperatures were required. It would be advantageous to have a method of integrated circuit burn-in which grouped the circuits which were formed on the same wafer together.
Accordingly it is an object of the present invention to provide a method of burning in integrated circuits in wafer form.
It is another object of the present invention to provide a method of burning in integrated circuits which requires little floor space.
It is another object of the present invention to provide a method for burning in wafers which reduces the power and time required for burn-in.
It is still another object of the present invention to provide a method of burning in integrated circuits which eliminates manual loading and unloading of boards.
It is another object of the present invention to provide a method of burning in integrated circuits which improves package quality.